- JEDEC Standard
- Bandwidth(max): 5.3GB/s
- Date Rate: 667MHz
- Double Data Rate architecture
- Differential Data Strobe (DQS)
- Differential clock inputs (CK and /CK)
- MRS cycle with address key programs
- Edge aligned data output, center aligned data input
- 2 banks to be operated simultaneously or independently
- Serial Presence Detect with EEPROM
